Together with our academic partners we develop new methodologies for verifying/validating integrated circuits and for ensuring their reliability over life-time.
Driven by the demands for more functionality, performance and reliability, the verification and validation of integrated circuits require new and innovative approaches to be able to meet the tight time-to-market requirements.
Together with our Austrian and international academic partner (like Alpen-Adria-University of Klagenfurt, Carinthia University of Applied Sciences, Graz University of Technology, Vienna University of Technology, University Milano Bicocca) we have developed competences and we continuously improve our knowledge in the following cutting edge research topics:
- Automotive system security. By understanding the requirements of system security in automotive applications – especially regarding new ADAS (Advanced Driver Assistance Systems) and autonomous driving – we can proactively determine the specific requirements for the next generation of integrated circuits.
- Measuring analog defect coverage by efficient fault injection simulations to ensure the quality of the integrated circuits delivered to the customer. Here a KAI representative is also member of the “IEEE Analog Test Coverage and Access Study Group” for the standardization of “Analog Defect Coverage”.
- Modelling of analog integrated circuits by means of a Neural Network. The time for the model generation can hereby be decreased significantly while keeping the benefits of simulation speed improvement associated with traditional modeling techniques.
- Developing highly efficient DfT (Design for Test) measures to decrease the ATE test time and to increase the test coverage.
- Building application demonstrators to validate integrated circuits in an application like environment. By evaluating integrated circuits early in the development cycle using an application like environment, feedback to the design team can be provided before the circuit is tested in a real system environment.
- Estimation of realistic FIT rates (Failure-in-time) early in the product development using stress test and field return data of related products.
- Integrated age detection circuits. By monitoring the “health” of integrated circuits continuously in the field, we can provide an early warning of a chip failure and initiate a replacement of the component before actual failure.
- How can I ensure, that my ATE test program has the required test coverage and detects all possible random manufacturing defects?
- How can I make sure, that my specification meets the application requirements?
- What are the requirements for the next generation of semiconductor devices for autonomous driving?
- How can I minimize my ATE test time while still keeping the required test coverage?