The project was successfully finished on 30 September 2016.
Temperature variations during operation cause stresses in semiconductor devices due to differences in the coefficients of thermal expansion (CTE) between film and substrate. Measurement of these stresses is important for proper device design and the main topic of this project. The wafer curvature method is a common technique to quantify the stresses for thin films on substrates, but suffers the drawback that generally the applied strain rates (applied strain/time) are six magnitudes lower than the ones occurring during device service. As material properties are strain rate dependent an extrapolation of measurement results over several orders of magnitude is difficult. This necessitates the determination of the stresses at strain rates similar to the ones occurring during service.
Proposed solution: Development and installation of a high speed wafer curvature measurement system to investigate the influence of high strain rates on metallic thin films on Silicon substrates.
A new testing device based on the common wafer curvature measurement method, using two parallel laser beams (see Figure 1), is built-up. The setup takes into account the small sample size of the semiconductor specimens and works with a high-speed camera instead of a standard CCD camera to allow a 10 times faster image acquisition rate. This should allow a stress measurement at high strain rates, which will be verified by measuring stresses of various thin films on silicon substrates.
The project started in April 2013 within the large European research project EPPL (Enhanced Power Pilot Line). Within this project, KAI was the work package leader for WP2 “Technology and Demonstrator Research”.
During this time KAI, developed competences in these areas:
- High speed measurements with wafer curvature method
- Strain rate dependence of metallic films
- Thermomechanical measurements on metallic films